Items where Author is "Steven, G.B."
Number of items: 28.
Two-level branch prediction using neural networks. (2003)
C. Egan,
G.B. Steven,
P. Quick,
R. Anguera,
F.L. Steven
and
L. Vintan
Cached Two-Level Adaptive Branch Predictors with Multiple Stages. (2002)
C. Egan,
G.B. Steven
and
L. Vintan
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Adding static data dependence collapsing to a high-performance instruction scheduler. (2001)
F.L. Steven,
C. Egan,
R. Potter
and
G.B. Steven
Applying Caching to Two-Level Adaptive Branch Prediction. (2001)
C. Egan,
G.B. Steven,
W. Shim
and
L. Vintan
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Dynamic branch prediction using neural networks. (2001)
G.B. Steven,
R. Anguera,
C. Egan,
F.L. Steven
and
L. Vintan
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A cost-effective two-level adaptive branch predictor. (2001)
G.B. Steven,
C. Egan,
W. Shim
and
L. Vintan
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A superscalar architecture to exploit instruction level parallelism. (1997)
G.B. Steven,
B. Christianson,
R. Collins,
F.L. Steven
and
R. Potter
Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture. (1997)
C. Egan,
F.L. Steven
and
G.B. Steven
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Instruction scheduling for a superscalar architecture. (1996)
R. Collins
and
G.B. Steven
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An introduction to the Hatfield superscalar architecture. (1996)
G.B. Steven,
B. Christianson,
R. Collins,
R. Potter
and
F.L. Steven
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Hades - towards the design of an asynchronous superscalar processor. (1995)
C.J. Elston,
B. Christianson,
P. Findlay
and
G.B. Steven
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HARP: a statically scheduled multiple-instruction-issue architecture and its compiler. (1994)
R.G. Adams,
S.M. Gray
and
G.B. Steven
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Using a resource limited instruction scheduler to evaluate the iHARP processor. (1994)
F.L. Steven,
G.B. Steven
and
L. Wang
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An evaluation of the iHARP multiple instruction issue processor. (1994)
F.L. Steven,
G.B. Steven
and
L. Wang
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An explicitly declared delayed-branch mechanism for a superscalar architecture. (1994)
R. Collins
and
G.B. Steven
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Addressing Mechanisms for VLIW and Superscalar Processors. (1993)
F.L. Steven,
R.G. Adams,
G.B. Steven,
L. Wang
and
D. Whale
Modelling superscalar pipelines with finite state machines. (1993)
G.B. Steven
and
L. Vintan
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Static Instruction Scheduling for the HARP Multiple-Instruction-Issue Architecture. (1993)
S.M. Gray,
R.G. Adams,
G.J. Green
and
G.B. Steven
An evaluation of the architectural features of the iHARP processor. (1993)
F.L. Steven,
G.B. Steven
and
L. Wang
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Static instruction scheduling for the HARP multiple-instruction-issue architecture. (1992)
S.M. Gray,
R.G. Adams,
G.J. Green
and
G.B. Steven
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iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features. (1992)
S.A. Trainis,
P. Findlay,
G.B. Steven,
R.G. Adams
and
D. McHale
iHarp: a Multiple Instruction Issue Processor. (1992)
G.B. Steven,
R.G. Adams,
P. Findlay
and
S.A. Trainis
HARP: a VLIW RISC processor. (1991)
P. Findlay,
S.A. Trainis,
G.B. Steven
and
R.G. Adams
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A Parallel Pipelined Processor with Conditional Instruction Execution. (1991)
R.G. Adams
and
G.B. Steven
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The development of iHARP: a multiple instruction issue processor chip. (1991)
G.B. Steven,
R.G. Adams,
P. Findlay
and
S.A. Trainis
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Address and data register separation of the M68000 family. (1990)
F.L. Williams
and
G.B. Steven
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Integer division by small constants. (1990)
G.B. Steven
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HARP: A Parallel Pipelined RISC Processor. (1989)
G.B. Steven,
S.M. Gray
and
R.G. Adams